1. Field of the Invention
The invention relates to computer systems, and more particularly to computer systems having cache memory systems.
2. Description of the Related Art
Personal computer systems are becoming quite advanced and are approaching the capabilities of mainframe and minicomputers of a few years ago. Personal computers compatible with those developed by International Business Machines Corporation (IBM) utilize microprocessors and related parts developed by Intel Corporation (Intel). These microprocessors include the 8088, the 8086, the 80286, and most recently the 80386. Each of these devices has had a greater performance than its predecessor, because of increasing clock speeds, increasing word sizes, increasing memory size and many other factors.
The speeds available for the 80386, the 32 bit processor, are such that cost effective memory devices limit the performance of the personal computer. The memory devices are relatively slow so that wait states must be added to memory accesses so that the data is properly read or written. Thus the processor can not run at full speed. Memory devices which would allow the processor to run at full speed are available, but are cost prohibitive in most cases. To resolve this problem Intel developed the 82385, a cache memory controller for use with the 80386. A cache memory is a small area of very fast memory from which the processor can run at full speed. Only a small amount of this memory is used for cost reasons, so the cache controller has the duty of controlling accesses to the main memory or the cache memory. When the data is present in the cache memory the controller uses the cache, while if the data is present only in main memory, the data is retrieved from the main memory, provided to the processor and stored in the cache for later use. By proper sizing of the cache memory and the cache algorithm, hit rates, that is, references to the cache memory only, may reach into the area of 90% or greater. The 82385 is such a controller. Details of the operation of the 80386 and the 82385 are available in various books published by Intel, such as the Microprocessor and Peripheral Handbook, Volume 1, Microprocessor, 1988, and by other parties. Familiarity with the 80386 and 82385 will be presumed in this specification.
There are two signals of interest relating to the 82385 in this description. The first signal is the NCA* or noncachable address signal. This signal is an input to the 82385 and is used to indicate that the address being presented by the 80386 is noncachable, that is, a copy of the data should not be stored in the cache memory. This occurs for several reasons, one being that the location is not a read/write location as in the case of a mapped peripheral register. When this signal is lowered at the appropriate time, the 82385 understands that the address is noncachable and always passes the cycle on to the main memory, without referencing the various tables in the 82385. This signal thus was originally suitable to be used as a signal to disable the functioning of the cache memory system. The NCA* signal was held low and all operations were passed through to the main memory. This technique worked satisfactorily for the earlier 16 MHz and 20 MHz versions of the 82385. However, in certain 25 MHz, all faster and certain other newer versions of the 82385 the timing of the signal was changed. The internal sampling time of the signal was delayed for other reasons.
A possible cache coherency problem developed. The cache is not coherent if different data values can exist at a memory location and the copy of that location in the cache memory. If the NCA* signal was utilized in the previous manner, a coherency problem could develop as follows. The cache system would be enabled and a particular memory location would be read. This loads the data value into the cache memory. The cache system would then be turned off, by driving the NCA* signal low for all cycles. A write operation would then be performed to the particular memory location. The data would be properly stored in the main memory, but would not be stored in the cache memory because the timing change did not leave sufficient time for the cache controller to update the cache memory. The cache system would then be turned on by releasing the NCA* signal. Thus the data would be different in the two locations but the internal valid flag bit in the 82385 would still be set. Thus a coherency problem could exist.
The other signal of interest is the FLUSH signal, which is used to flush the entire cache memory. This is simply done by the 82385 by clearing all the valid bits. The specifications for the 82385 indicate that the FLUSH input must be held high for 4 CLK cycles to insure that all the valid bits have been cleared. If the FLUSH input is high past the 4 cycles, any accesses to the cache will be considered misses and transferred to the main memory and the cache will not be updated. Intel notes that the use of the FLUSH input as a coherency mechanism may impact software transparency.